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| may 2010 doc id 13883 rev 3 1/20 AN2620 application note 3 a high-frequency synchronous 900 khz step-down converter based on the st1s10 introduction the st1s10 is a step-down dc-dc converter with an optimized inhibit function for powering high-voltage lcd applications and low-voltage digital core hdd applications. generally, it replaces the high current linear solution wh en high power dissipation is a problem. it provides up to 3 a over an input voltage range of 2.5 v to 18 v and synchronous rectification saves the external schottky diode. a high internal switching frequency (0.9 mhz) allows it to use tiny surface-mount components, as well as the resistor divider, to set the output voltage value. only an inductor and 3 capacitors are required. the current pwm mode architecture and stable operation with low e.s.r smd cera mic capacitors results in low, predictable output ripple. to maximize the power conversion efficiency in light load, the regulator can work in burst mode automatically. the device can operate in pwm mode at a fixed frequency or synchronized to an external frequency. it switches at a frequency of 900 khz when sync is connected to ground or a fixed voltage (less than 5.5 v) and synchronizes the switching frequency between 400 khz to 1.2 mhz from the external clock that is applied to sync. a thermal shutdown circuit is integr ated and activates at 150 c. cycle-by-cycle current limitation provides protection against shorted outputs. the on-chip 260 s power-on reset ensures the proper operation when switching on the power supply. the quiescent current is less than 6 a in the inhibit state. the device is available in mlp4x4 and so-8 epad packages. figure 1. simplified schematic www.st.com
contents AN2620 2/20 doc id 13883 rev 3 contents 1 application information component selection . . . . . . . . . . . . . . . . . . . . 4 1.1 input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 short-circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 board usage recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 external component selection for the st1s10 demonstration board . . . . 13 4.2 inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3 capacitors selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4 heavy capacitive load condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.5 low output voltage (vout < 2.5 v) and 2.5 v < vin < 8 v . . . . . . . . . . . . . 14 4.6 layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 layout thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 AN2620 list of figures doc id 13883 rev 3 3/20 list of figures figure 1. simplified schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2. st1s10 demonstration board typical diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3. demonstration board layout st1s10 mlp package - top side . . . . . . . . . . . . . . . . . . . . . . 10 figure 4. demonstration board layout st1s10 mlp package - bottom side . . . . . . . . . . . . . . . . . . . 10 figure 5. demonstration board layout st1s10 so-8 epad - top side . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 6. demonstration board layout st1s10 so-8 epad package - bottom side. . . . . . . . . . . . . . 11 figure 7. enable jumper selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 8. external synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 9. st1s10 application schematic for heavy capacitive load . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 10. st1s10 application schematic for low output voltage (vout < 2.5 v) and 2.5 v < vin < 8 v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 11. st1s10 application schematic for low output voltage (vout < 2.5 v) and 8 v < vin < 16 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 12. pcb layout suggestion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 13. pcb layout vin_a and vin_sw detail. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 figure 14. pcb layout details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 application information component selection AN2620 4/20 doc id 13883 rev 3 1 application information component selection 1.1 input capacitor the st1s10 features two v in pins: v in_sw for the power supply input voltage where the switching peak current is drawn, and v in_a to supply the st1s10 internal circuitry and drivers. the v in_sw input capacitor reduces the current peaks drawn from the input power supply and reduces switching noise in the ic. high power supply source impedance requires larger input capacitance. for the v in_sw input capacitor the rms current rating is a critical parameter that must be higher than the rms input current. the maximum rms input current can be calculated using the following equation: equation 1 where is the expected system efficiency, d is the duty cycle and i o the output dc current. this function reaches its maximum value at d = 0.5 and the equivalent rms current is equal to io divided by 2 (considering = 1). the maximum and minimum duty cycles are: equation 2 equation 3 where v f is the voltage drop across the internal nmos and v sw the voltage drop across the internal pdmos. considering the range d min to d max it is possible to determine the max i rms following through the input capacitor. a minimum value of 4.7 f for the v in_sw and a 0.1 f ceramic capacitor for the v in_a are suitable in most application conditions. a 10 f or higher ceramic capacitor for the v in_sw and a 1 f (v in_a ) are advisable in case of higher power supply source impedance or where it is needed to have long wires between the power supply source and the v in pins. the above suggested higher input capacitors values are also advisable in case of high output capacitive load which can impact the switching peak current drawn from the input capacitor during the startup transient. it is also advisable to use ceramic capacitors with a voltage rating in the range of 1.5 times the maximum input voltage. the input capacitors should be located as close as possible to the v in pins. different capacitors can be considered: electrolytic capacitors. these are the most commonly used because they are the least expensive and are available with a wide range of rms current ratings. the only i rms i o d 2d 2 ? -------------- - ? d 2 ------ - + ? = d max v out v f + v inmin v sw ? ----------------------------------- = d min v out v f + v inmax v sw ? ------------------------------------- = AN2620 application information component selection doc id 13883 rev 3 5/20 drawback is that, considering a requested ripple current rating, they are physically larger than other capacitors. ceramic capacitors. if available for the requested value and voltage rating, these capacitors usually have a higher rms curr ent rating for a given physical dimension (due to the very low esr). the drawback is the quite high cost. tantalum capacitor. very good tantalum capacitors are becoming available, with very low esr and small size. the only problem is that they occasionally can burn if subjected to very high current during the charge. so, it is better to avoid this type of capacitor for the input filter of the device. in fact, they can be subjected to high surge current when connected to the power supply. 1.2 output capacitor the output capacitor is very important in satisfying the output voltage ripple requirement. using a small inductor value to reduce the size of the choke is useful, but increases the current ripple. so, to reduce the output voltage ripple, a low esr capacitor is required. the most important parameters for the output capacitor are the capacitance, the esr and the voltage rating. the capacitance and the esr affect the contro l loop stability, the outpu t ripple voltage, and transient response of the regulator. the ripple due to the capacitance can be calculated by the following formula: equation 4 where f s is the pwm switching frequency and i sw is the inductor peak - to - peak switching current that can be calculated as: equation 5 where d is the duty cycle while the ripple due to the esr is given by: equation 6 use the above equations to define capacitor selection range, but final values should be verified by testing an evaluation circuit. lower esr ceramic capacitors are usually advi sable to reduce the output ripple voltage. capacitors with higher voltage ratings have lo wer esr values, providing lower output ripple voltage. also the capacitor esl value impacts the output ripple voltage, but ceramic capacitors usually have very low esl, making ripple volt ages due to the esl negligible. in order to reduce ripple voltages due to a parasitic inductive effect, keep the output capacitor connection paths as short as possible. v ripple c () 0.125 i sw ? f s c out ? -------------------------------- - = i sw v in v out ? () f s l ? ------------------------------ d ? = v ripple esr () i sw esr ? = application information component selection AN2620 6/20 doc id 13883 rev 3 the st1s10 has been designed to have the be st performances with ceramic capacitors. in typical application conditions a minimum value of 22 f ceramic capacitor is suggested on the output, but higher values are suitable considering that the control loop has been designed to properly work with a natural output lc frequency given by a 3.3 h inductor and 22 f output capacitor in the typical application (v in =12 v, v out =5 v). it is advisable to use ceramic capacitors with a voltage rating in the range of 1.5 times the maximum output voltage. 1.3 inductor the inductor value is very important because it fixes the ripple current flowing through the output capacitor. the ripple current is usually fixed at 20-40% of i omax , that is 0.6-1.2 a with i omax = 3 a. the inductor value is approximately obtained by the following formula: equation 7 where, t on is the on time of the internal switch, given by d t. for example, with v out = 3.3 v, v in = 5 v and i o = 0.45 a, the inductor value is about 2.8 h. the peak current thought the inductor is given by: equation 8 it can be seen that if the inductor value decreases, the peak current (that has to be lower than the current limit of the device) increases. so, for fixed the peak current, a higher value of the inductor allows a higher value for the output current. the st1s10 is designed to have maximum performance with a 3.3 h inductor value at 900 khz. the peak inductor current must be designed in order to not exceed the switching current limit. l v in v out ? i ------------------------- t on ? = i pk i o i 2 ---- - + = i sat i pk AN2620 thermal considerations doc id 13883 rev 3 7/20 2 thermal considerations the dissipated power of the device is related to three different sources: switch losses due to the non-negligible r ds(on) . these are equal to: equation 9 equation 10 where, d is the duty cycle of the application. note that the duty cycle is theoretically given by the ratio between v out and v in , but in practical terms is quite higher than this value to compensate the losses of the overall application. due to this reason, the switch losses related to the r ds(on) increase compared to the ideal case. switch losses due to its turn-on and off. these are given by the following relationship: equation 11 where t on and t off are the overlap times of the voltage across the power switch and the current flowing into it during the turn-on and turn-off phases. t sw is the equivalent switching time (typ. 30 ns). quiescent current losses equation 12 where i q is the quiescent current. the junction temperature of device is: equation 13 where t a is the ambient temperature and rth j-a is the thermal resistance junction-to- ambient. p onp r ds on () p i 2 out d ?? = - - p onn r ds on () n i 2 out 1d ? () ?? = - - p q v in i q ? = t j t a rth ja ? p tot ? + = short-circuit protection AN2620 8/20 doc id 13883 rev 3 3 short-circuit protection in short condition, the st1s10 has two short protection functions to avoid a damaged device. overcurrent protection (ocp). the st1s10 dc-dc converter is provided with a switch overcurrent protection. if the switch current limit is reached, in order to protect the application and the internal power switc hes and bonding wires, the device is immediately shut down and kept in this condition for a t off period time (t off = 135 s typ) and turns on again for a t on period (t on = 22 s typ with typical application conditions). this operation is repeated cycle by cycle. normal operation is resumed when no overcurrent is detected. overvoltage protection (ovp). in order to protect the whole application and reduce the total power dissipation during an overload or an output short-circuit condition, the device is provided with a dynamic short-circuit protection which works by internally monitoring the v fb (feedback voltage). in case of overload or output short-circuit, if the v out voltage is reduced causing the feedback voltage (v fb ) to drop below 0.3 v typ, the device goes in shutdown for t off time (t off = 288 s typ) and turns on again for a t on period (t on = 130 s typ). this operation is repeat ed cycle by cycle. normal operation is resumed when no overload is detected (v fb > 0.3 v typ) for a full t on period. this dynamic operation can greatly reduce the po wer dissipation in overload condition, still ensuring excellent power-on startup, in most conditions. AN2620 board usage recommendation doc id 13883 rev 3 9/20 4 board usage recommendation the board shown in figure 2 is provided with a kelvin conn ection which means that for each pin two lines are available, one used to supply or sink current and the other one used to perform the needed measurement. the st1s10 inhibit pin should be connected to gnd or v in , by a jumper, in order to turn off or on the device. if the sync pin is not used, it is better to connect to gnd to avoid input noise to the device. figure 2. st1s10 demonstration board typical diagram 6 3 7 l1 c1 1 3 2 r2 r1 1 r3 c3 2 5 4-8 vout sync vin vin gnd gnd 2-3=inh-off 1-2=inh-on ic1 epad* c2 r1=10 k r2=2 k r3=10 k c1=4.7f c2=22f c3=0.1f l1=3.3 h ic1=st1s10 *epad connected to gnd gnd gnd vout 12vin 5vout board usage recommendation AN2620 10/20 doc id 13883 rev 3 figure 3. demonstration board layout st1s10 mlp package - top side figure 4. demonstration board layout st1s10 mlp package - bottom side AN2620 board usage recommendation doc id 13883 rev 3 11/20 figure 5. demonstration board layout st1s10 so-8 epad - top side figure 6. demonstration board layout st1s10 so-8 epad package - bottom side board usage recommendation AN2620 12/20 doc id 13883 rev 3 figure 7. enable jumper selection figure 8. external synchronization AN2620 board usage recommendation doc id 13883 rev 3 13/20 4.1 external component selectio n for the st1s10 demonstration board figure 2 shows the typical application used to obtain an output voltage of 5 v. in order to obtain the needed output voltage we must choose the resistor divider according to the following formula: equation 14 where v fb = 0.8 v and r2 suggested value is ~2 k . 4.2 inductor selection due to the high frequency (900 khz) it is possible to use a very small inductor value. we tested our device with an inductor value of 3.3 h with very good efficiency performances. as the device is able to provide an operative output current of 3 a, we strongly recommend using inductors able to manage at least 4.4 a. 4.3 capacitors selection it is possible to use any x5r or x7r ceramic capacitor c1 = 4.7 f (ceramic) or higher c2 = 22 f (ceramic) or higher, esr=10 ~ 100 m range c3 = 0.1 f (ceramic) or higher it is possible to put several capacitors in parallel in order to reduce the equivalent series resistor and improve the ripple present in the output voltage. 4.4 heavy capacitive load condition thanks to the ocp and ovp circuit, the st1s10 is strongly protected against short-circuit and overload damages. however, a highly capacitive load on the output may cause a difficult startup. this can be solved by using the modified application circuit shown in figure 9 in which a minimum of 10 f for c1 and a 4.7 f ceramic capacitor for c3 are used. moreover, for c load >100 f, it is needed to add the c4 capacitor in parallel to the upper voltage divider resistor (r1) as shown in figure 9 . the suggested value for c4 is 4.7 nf ~ 47 nf. note that the c4 may impact the control loop response and should be added only when a capacitive load higher than 100 f is present at all times. if the high capacitive load is variable or not present at any time, in addition to c4 it is advisable to increase the output ceramic capacitor c2 from 22 f to 47 f (or use 2 x 22 f capacitors in parallel). also in this case it is advisable to further increase th e input capacitors with a minimum of 10 f for c1 and a 4.7 f ceramic capacitor for c3 as shown in figure 10 . v out v fb 1 r1 r2 ------- - + ? = board usage recommendation AN2620 14/20 doc id 13883 rev 3 figure 9. st1s10 application schematic for heavy capacitive load 4.5 low output voltage (v out < 2.5 v) and 2.5 v < v in < 8 v for applications with lower output voltage levels (v out < 2.5 v) the output capacitance and the inductor values should be selected in a way that improves the dc-dc control loop behavior. in this output condition two cases must be considered: v in > 8 v and v in < 8 v. for v in < 8 v the use of 2 x 22 f capacitors in parallel to the output is recommended, as shown in figure 10 . for v in > 8 v, a 100 f electrolytic capacitor with esr < 0.1 should be added in parallel to the 2 x 22 f output capacitors as shown in figure 11 . figure 10. st1s10 application schematic for low output voltage (v out < 2.5 v) and 2.5 v < v in < 8 v 6 3 7 l1 c1 1 3 2 r2 r1 1 r3 c3 254-8 v out sync v in v in gnd gnd 2-3 = inh-off 1-2 = inh-on ic1 epad* r1 = 100 k r2 = 20 k r3 = 10 k c1 = 4.7 f c2 = 22 f c3 = 0.1~4.7 f l1 = 3.3 h ic1 = st1s10 *epad connected to gnd gnd gnd v out 12 v in 5 v out c2 c4 = 4.7 nf c4 6 3 7 l1 c1 1 3 2 r2 r1 1 r3 c3 254-8 v out sync v in v in gnd gnd 2-3 = inh-off 1-2 = inh-on ic1 epad* r1 = 100 k r2 = 20 k r3 = 10 k c1 = 4.7 f c2 = 22 f c3 = 0.1~4.7 f l1 = 3.3 h ic1 = st1s10 *epad connected to gnd gnd gnd v out 12 v in 5 v out c2 c4 = 4.7 nf c4 6 3 7 l1 c1 1 3 2 r2 r1 1 r3 c3 254-8 vout sync vin vin gnd gnd 2-3=inh-off 1-2=inh-on ic1 epad* c2 r1=* r2=2 k r3=10 k c1=2*4.7 f or 10 f c2=2*22 f c3=0.47~1 f gnd gnd vout <2.5vout 8 AN2620 board usage recommendation doc id 13883 rev 3 17/20 figure 13. pcb layout vin_a and vin_sw detail figure 14. pcb layout details equation 15 the trace connecting pin 1 (vin_a) and pin 2 (en) to input supply should start very close to pin 6 (vin_sw) to minimize voltage drop trace to pin 6 (vin_sw) must be thick (high current) the trace connecting pin 1 (vin_a) and pin 2 (en) to input supply should start very close to pin 6 (vin_sw) to minimize voltage drop trace to pin 6 (vin_sw) must be thick (high current) i in i powerground i out i device i c1 i c2 +++ = = layout thermal considerations AN2620 18/20 doc id 13883 rev 3 5 layout thermal considerations the leadframe die pad of the st1s10 is exposed at the bottom of the package and must be soldered directly to a properly designed thermal pad on the pcb (ground copper area used as a heat sink). the addition of thermal vias from the thermal pad to an internal or bottom ground plane helps to increase the power dissipation. AN2620 revision history doc id 13883 rev 3 19/20 6 revision history table 2. document revision history date revision changes 20-aug-2008 1 initial release 04-nov-2008 2 title changed on cover page to improve readability 13-may-2010 3 modified: figure 9 on page 14 , figure 12 and figure 13 on page 17 AN2620 20/20 doc id 13883 rev 3 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2010 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com |
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